Nanometer technologies enable manufacturing of very large system-on-chip (SoC) designs that have many cores originating from a variety of sources. One of the main reasons for the growing popularity of SoC designs is the ability to reuse the cores that have been independently designed and verified. Modern multicore SoC architectures have the ability to encapsulate many heterogeneous IP cores running at different clock rates with different power requirements and multiple power-supply voltage levels. Meanwhile, the test constraints at the SoC level, such as the total available test pins, acceptable peak and average test power, DFT layout/routing limit etc, must be satisfied. Many SoC-based test schemes proposed so far utilize dedicated instrumentation including test access mechanisms (TAM) and test wrappers, plus various test pattern scheduling algorithms. TAMs are typically used to transfer test data between the SoC pins and the embedded cores, while test wrappers form the interface between the core and the SoC environment. Test scheduling algorithms are applied to minimize SoC test time. A well-designed TAM and test scheduling can dynamically assign a fraction of the ATE interface capacity to each core. For example, the test pins at different cores could share the same pins at the SoC level in a time-division-multiplexing manner. This allows trade-offs between the test application time, volume of scan test data, test pin count, and interface design complexity.
Meanwhile, scan test compression technologies, such as the Embedded Deterministic Test (EDT), are widely used for logic test of SoCs. Each core usually has its own compression logic developed in isolation from the rest of the design, and the compression can be used for testing the core when it is embedded in the SoC.
In the core-based SoC testing, ATPG (Automatic Test Pattern Generation) is usually performed for each wrapped core, and the core level patterns are mapped to the SoC level, which may be referred to as hierarchical pattern retargeting. Hierarchical pattern retargeting has several benefits compared to running ATPG at the SoC level such as small memory footprint and CPU time and pattern generation without full netlists.
In practice, a SoC may have many cores. Some cores could be large and other cores could be small. Wrapping each small core for hierarchical pattern retargeting may not be an efficient solution. Small cores are often grouped into one unit and one wrapper is inserted around this group of small cores. Under this situation, ATPG has to be run on top of a group of cores inside one wrapper and the generated patterns for this group of cores are mapped to the SoC level. This, called hybrid test flow in this paper, includes ATPG on one or multiple cores followed by hierarchical pattern retargeting.
Running ATPG on a group of cores has its own advantages compared to the hierarchical pattern retargeting on each core in this group: core wrapping is not required; and more optimized pattern counts may be obtained due to ATPG native static and dynamic compaction on a bigger set of fault population. Even in a large core without any embedded cores, it is possible to have multiple modules/blocks, each of which has its own compression logic. Modular compression logic is primarily used in two situations: 1) To reduce routing overhead by using local compression logic rather than global compression logic; and 2) If a core has multiple power domains, each power domain may have its own compression logic to minimize the number of signals crossing power domain boundaries, reducing the number of power isolation cells and/or level shifters. In this disclosure, the term “circuit block” is used to represent a part of a circuit that has its own test compression logic. A circuit block may be a core or a part of a core.
The limited number of input/output channels for test stimuli and test response data remains as a constraint for running ATPG on a group of circuit blocks. Identical circuit block instances can share input channels for scan stimuli. It is the increasing number of non-identical circuit blocks that creates the bottleneck and limits the bandwidth that can be provided to each circuit blocks. Because the number of test input channels is very limited for a circuit block, its effective compression ratio may drop due to insufficient encoding capacity. It is thus desirable to develop techniques for testing circuits having non-identical circuit blocks based on channel sharing.